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integrated circuit systems, inc. ics94228 0447e?05/07/04 block diagram functionality pin configuration 48-pin 300mil ssop recommended application: via kt266 style chipset output features: 1 - differential pair open drain cpu clocks @ 2.7v 1 - differential pair push-pull cpu clocks @ 2.5v 11 - pci including 1 free running and 1 early @ 3.3v 1 - 48mhz, @ 3.3v fixed 1 - 24/48mhz @ 3.3v 3 - ref @ 3.3v, 14.318mhz. features: programmable output frequency. programmable output rise/fall time. programmable slew and skew control for cpuclk, pciclk, agp, ref, 48mhz and 24_48mhz. real time system reset output. spread spectrum for emi control typically by 7db to 8db, with programmable spread percentage. watchdog timer technology to reset system if over-clocking causes malfunction. uses external 14.318mhz crystal. skew specifications: ? cpu - cpu: <200ps pci - pci: <500ps cpu (early - pci: min=1.0ns, max=2.6ns cpu cycle to cycle jitter: <250ps programmable system clock chip for amd - k7? processor * internal pull-up resistor of 120k to vdd sel24_48# pll2 pll1 spread spectrum 48mhz (1:0) 24_48mhz pciclk (8:0) agp (2:0) pciclk_f ref_f pciclk9_e sreset# 3 9 2 2 x1 x2 xtal osc cpu divder cpu divder pci divder agp divder stop stop stop stop s data sclk fs (3:0) pd# pci_stop# cpu_stop# agp_stop# ref_stop# control logic config. reg. / 2 ref (1:0) cpuclkt0 cpuclkc0 cpuclk_cst0 cpuclk_csc0 3 s f2 s f1 s f0 s f u p c ) z h m ( p g a ) z h m ( k l c i c p ) z h m ( 0000 3 3 . 3 3 28 7 . 7 78 8 . 8 3 000 1 0 0 . 0 2 23 3 . 3 77 6 . 6 3 00 10 0 0 . 0 1 20 0 . 0 70 0 . 5 3 00 11 0 0 . 0 0 27 6 . 6 63 3 . 3 3 0100 0 0 . 0 9 10 0 . 6 70 0 . 8 3 0101 0 0 . 0 8 10 0 . 2 70 0 . 6 3 0110 0 0 . 0 7 10 0 . 8 60 0 . 4 3 0 111 0 0 . 0 5 10 0 . 5 70 5 . 7 3 1000 0 0 . 0 4 10 0 . 0 70 0 . 5 3 10 0 1 0 0 . 0 2 10 0 . 0 60 0 . 0 3 10 10 0 0 . 0 1 10 0 . 6 60 0 . 3 3 10 1 1 7 6 . 6 67 6 . 6 63 3 . 3 3 1100 0 0 . 0 0 27 6 . 6 63 3 . 3 3 110 1 7 6 . 6 6 17 6 . 6 63 3 . 3 3 1110 0 0 . 0 0 17 6 . 6 63 3 . 3 3 1111 3 3 . 3 3 17 6 . 6 63 3 . 3 3 vddref gnd x1 x2 avdd48 *fs2/48mhz *fs3/24_48mhz gnd pciclk_f *sel24_48#/pciclk0 pciclk1 gnd pciclk2 pciclk3 vddpci pciclk4 pciclk5 pciclk6 gnd pciclk7 pcilck8 pciclk9_e vddpci sreset# ref0/ ref1/fs1* ref_f ref_stop#* agp_stop#* gnd cpuclkt0 cpuclkc0 vddl cpuclk_cst0 cpuclk_csc0 gnd cpu_stop#* pci_stop#* pd#* avdd agnd s data sclk gnd agp2 agp1 agp0 vddagp fs0* ics9422 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
2 ics94228 0447e?05/07/04 pin descriptions notes: 1: internal pull-up resistor of 120k to 3.3v on indicated inputs 2: bidirectional input/output pins, input logic levels are latched at internal power-on-reset. use 10kohm resistor to program logic hi to vdd or gnd for logic low. r e b m u n n i pe m a n n i pe p y tn o i t p i r c s e d , 5 2 , 3 2 , 5 1 , 1d d vr w pv 3 . 3 l a n i m o n , y l p p u s r e w o p , 9 1 , 2 1 , 8 , 2 3 4 , 7 3 , 9 2 d n gr w pd n u o r g 31 xn i 2 x m o r f r o t s i s e r k c a b d e e f d n a ) f p 6 3 ( p a c d a o l l a n r e t n i s a h , t u p n i l a t s y r c 42 xt u o ) f p 6 3 ( p a c d a o l l a n r e t n i s a h . z h m 8 1 3 . 4 1 y l l a n i m o n , t u p t u o l a t s y r c 58 4 d d v ar w pv 3 . 3 l a n i m o n , y l p p u s r e w o p 6 2 s f 2 , 1 n it u p n i d e h c t a l . n i p t c e l e s y c n e u q e r f z h m 8 4t u op o t s _ f e r y b e l b a p p o t s , k c o l c t u p t u o z h m 8 4 7 3 s f 2 , 1 n it u p n i d e h c t a l . n i p t c e l e s y c n e u q e r f z h m 8 4 _ 4 2t u op o t s _ f e r y b e l b a p p o t s , t u p t u o k c o l c z h m 8 4 r o 4 2 9f _ k l c i c pt u o . t n e m e g a n a m r e w o p r o f # p o t s _ i c p y b d e t c e f f a t o n k c o l c i c p g n i n n u r e e r f 0 1 # 8 4 _ 4 2 l e s 2 , 1 n it u p t u o 7 n i p r o f z h m 8 4 r o 4 2 t c e l e s o t t u p n i c i g o l 0 k l c i c pt u ot u p t u o k c o l c i c p , 7 1 , 8 1 , 0 2 , 1 2 1 1 , 3 1 , 4 1 , 6 1 ) 1 : 8 ( k l c i c pt u o. s t u p t u o k c o l c i c p 2 2e _ 9 k l c i c pt u o . # p o t s _ i c p y b d e p p o t s e b n a c . s n 2 y b s k c o l c i c p l a r e n e g s d a e l . k c o l c i c p y l r a e 4 2# t e s e r s 1 t u o . w o l e v i t c a s i l a n g i s s i h t . t u o e m i t r e m t g o d h c t a w r o f l a n g i s t e s e r m e t s y s e m i t l a e r 6 2 , 7 2 , 8 2) 0 : 2 ( p g at u os t u p t u o k c o l c p g a 0 3k l c sn ii f o t u p n i k c o l c 2 t u p n i t n a r e l o t v 5 , t u p n i c 1 3a t a d so / ii r o f n i p a t a d 2 t n a r e l o t v 5 y r t i u c r i c c 2 3d n g ar w pd n u o r g g o l a n a 3 3d d v ar w pv 3 . 3 l a n i m o n , y l p p u s r e w o p 4 3# d pn i w o l a o t n i e c i v e d e h t n w o d r e w o p o t d e s u n i p t u p n i w o l e v i t c a s u o n o r h c n y s a e r a l a t s y r c e h t d n a o c v e h t d n a d e l b a s i d e r a s k c o l c l a n r e t n i e h t . e t a t s r e w o p . s m 3 n a h t r e t a e r g e b t o n l l i w n w o d r e w o p e h t f o y c n e t a l e h t . d e p p o t s 5 3# p o t s _ i c pn i w o l t u p n i n e h w , l e v e l 0 c i g o l t a s k c o l c f _ k l c i c p e h t s e d i s e b s k l c i c p l l a s p o t s 6 3# p o t s _ u p c 2 , 1 n i c i g o l t a s k c o l c s c _ c k l c u c & c k l c u p c , t k l c u p c s t l a h t u p n i s u o n o r h c n y s a s i h t . w o l n e v i r d n e h w l e v e l " 0 " 8 30 c s c _ k l c u p ct u o . ) l l u p - h s u p ( t e s p i h c t u p t u o r i a p l a i t n e r e f f i d f o k c o l c " y r a t n e m e l p m o c " 9 30 t s c _ k l c u p ct u o. ) l l u p - h s u p ( t e s p i h c t u p t u o u p c r i a p l a i t n e r e f f i d f o k c o l c " e u r t " 0 4l d d vr w pv 5 . 2 l a n i m o n , s k l c u p c r o f y l p p u s r e w o p 2 40 t k l c u p ct u o n a d e e n s t u p t u o n i a r d n e p o e s e h t . t u p t u o u p c r i a p l a i t n e r e f f i d f o k c o l c " e u r t " . ) n i a r d n e p o ( p u - l l u p v 5 . 1 l a n r e t x e 1 40 c k l c u p ct u o s t u p t u o n i a r d n e p o e s e h t . t u p t u o u p c r i a p l a i t n e r e f f i d f o k c o l c " y r a t n e m e l p m o c " . ) n i a r d n e p o ( p u - l l u p v 5 . 1 l a n r e t x e n a d e e n 4 4# p o t s _ p g an iw o l t u p n i n e h w , l e v e l 0 c i g o l t a s k c o l c p g a l l a s p o t s 5 4# p o t s _ f e rn i . w o l t u p n i n e h w , l e v e l 0 c i g o l t a s k c o l c z h m 8 4 / 4 2 d n a z h m 8 4 , f e r s p o t s 6 4f _ f e rt u o # p o t s _ f e r y b d e t c e t f f a t o n , . k c o l c e c n e r e f e r g n i n n u r e e r f z h m 8 1 3 . 4 1 7 4 1 s f 2 , 1 n it u p n i d e h c t a l . n i p t c e l e s y c n e u q e r f 1 f e rt u o. k c o l c e c n e r e f e r z h m 8 1 3 . 4 1 8 4 0 s f 2 , 1 n it u p n i d e h c t a l . n i p t c e l e s y c n e u q e r f 0 f e rt u o. k c o l c e c n e r e f e r z h m 8 1 3 . 4 1
3 ics94228 0447e?05/07/04 general description the ics94228 is a main clock synthesizer chip for amd-k7 based systems with via style chipset. this provides all clocks required for such a system. the ics94228 belongs to ics new generation of programmable system clock generators. it employs serial programming i 2 c interface as a vehicle for changing output functions, changing output frequency, configuring output strength, configuring output to output skew, changing spread spectrum amount, changing group divider ratio and dis/ enabling individual clocks. this device also has ics propriety 'watchdog timer' technology which will reset the frequency to a safe setting if the system become unstable from over clocking. sreset# signal description the sreset# signal from ics94228 system clock generator is a real time active low pulse that can be used to reset the system. the open-drain nch output reset# pin needs to be tied to the system reset line which has a pull-up resistor. when activated, the sreset# output will be driven to a low with a 32ms pulse width.
4 ics94228 0447e?05/07/04 general i 2 c serial interface information for the ics94228 how to write: ? controller (host) sends a start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends a dummy command code ics clock will acknowledge controller (host) sends a dummy byte count ics clock will acknowledge controller (host) starts sending byte 0 through byte 16 (see note 2) ics clock will acknowledge each byte one at a time controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the read address d3 (h) ics clock will acknowledge ics clock will send the byte count controller (host) acknowledges ics clock sends byte 0 through byte 6 (default) ics clock sends byte 0 through byte x (if x (h) was written to byte 6). controller (host) will need to acknowledge each byte controller (host) will send a stop bit *see notes on the following page . controller (host) ics (slave/receiver) start bit address d2 (h) ack dummy command code ack dummy byte count ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack byte 6 ack byte 14 ack byte 15 ack byte 16 ack stop bit how to write: controller (host) ics (slave/receiver) start bit address d3 (h) ack byte count ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack byte 6 ack if 7 h has been written to b6 byte 7 ack if 1a h has been written to b6 byte 14 ack if 1b h has been written to b6 byte 15 ack if 1c h has been written to b6 byte 16 ack stop bit how to read:
5 ics94228 0447e?05/07/04 1. the ics clock generator is a slave/receiver, i 2 c component. it can read back the data stored in the latches for verification. readback will support standard smbus controller protocol. the number of bytes to readback is defined by writing to byte 8. 2. when writing to byte 11 - 12, and byte 13 - 14, they must be written as a set. if for example, only byte 14 is written but not 15, neither byte 14 or 15 will load into the receiver. 3. the data transfer rate supported by this clock generator is 100k bits/sec or less (standard mode) 4. the input is operating at 3.3v logic levels. 5. the data byte format is 8 bit bytes. 6. to simplify the clock generator i 2 c interface, the protocol is set to use only block-writes from the controller. the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. the command code and byte count shown above must be sent, but the data is ignored for those two bytes. the data is loaded until a stop sequence is issued. 7. at power-on, all registers are set to a default condition, as shown. notes: brief i 2 c registers description for ics94228 programmable system frequency generator register name byte description pwd default functionality & frequency select register 0 output frequency, hardware / i 2 c frequency select, spread spectrum & output enable control register. see individual byte description output control registers 1, 2, 3 active / inactive output control registers/latch inputs read back. see individual byte description vendor id & revision id registers 5, 6, 7 byte 11 bit[7:4] is ics vendor id - 1001. other bits in this register designate device revision id of this part. see individual byte description byte count read back register 8 writing to this register will configure byte count and how many byte will be read back. do not write 00 h to this byte. 08 h watchdog enable register 4 writing to this register will configure the number of seconds for the watchdog timer to reset. 10 h watchdog control registers watchdog enable, watchdog status and programmable 'safe' frequency' can be configured in this register. 000,0000 vco control selection bit 4, 5 this bit select whether the output frequency is control by hardware/byte 0 configurations or byte 11&12 programming. 0 vco frequency control registers 9, 10 these registers control the dividers ratio into the phase detector and thus control the vco output frequency. depended on hardware/byte 0 configuration spread spectrum control registers 11, 12 these registers control the spread percentage amount. depended on hardware/byte 0 configuration group skews control registers 13, 14 increment or decrement the group skew amount as compared to the initial skew. see individual byte description output rise/fall time select registers 15, 16 these registers will control the output rise and fall time. see individual byte description
6 ics94228 0447e?05/07/04 byte0: functionality and frequency select register (default = 0) serial configuration command bitmap bit5 bit4 bit3 bit2 bit1 bit0 ssb1 ssb0 fs3 fs2 fs1 fs0 0 0 0000 233.33 77.78 38.88 +/- 0.25% center spread 0 0 0001 220.00 73.33 36.67 +/- 0.25% center spread 0 0 0010 210.00 70.00 35.00 +/- 0.25% center spread 0 0 0011 200.00 66.67 33.33 +/- 0.25% center spread 0 0 0100 190.00 76.00 38.00 +/- 0.25% center spread 0 0 0101 180.00 72.00 36.00 +/- 0.25% center spread 0 0 0110 170.00 68.00 34.00 +/- 0.25% center spread 0 0 0111 150.00 75.00 37.50 +/- 0.25% center spread 0 0 1000 140.00 70.00 35.00 +/- 0.25% center spread 0 0 1001 120.00 60.00 30.00 +/- 0.25% center spread 0 0 1010 110.00 66.00 33.00 +/- 0.25% center spread 0 0 1011 66.67 66.67 33.33+/- 0.25% center spread 0 0 1100 200.00 66.67 33.33 +/- 0.25% center spread 0 0 1101 166.67 66.67 33.33 +/- 0.25% center spread 0 0 1110 100.00 66.67 33.33 +/- 0.25% center spread 0 0 1111 133.33 66.67 33.33 +/- 0.25% center spread 0 1 0000 200.00 66.67 33.33 0 to -0.5% down spread 0 1 0001 166.67 66.67 33.33 0 to -0.5% down spread 0 1 0010 100.00 66.67 33.33 0 to -0.5% down spread 0 1 0011 133.33 66.67 33.33 0 to -0.5% down spread 1 0 0100 200.00 66.67 33.33 +/- 0.50% center spread 1 0 0101 166.67 66.67 33.33 +/- 0.50% center spread 1 0 0110 100.00 66.67 33.33 +/- 0.50% center spread 1 0 0111 133.33 66.67 33.33 +/- 0.50% center spread 1 1 1000 200.00 66.67 33.33 +/- 0.75% center spread 1 1 1001 166.67 66.67 33.33 +/- 0.75% center spread 1 1 1010 100.00 66.67 33.33 +/- 0.75% center spread 1 1 1011 133.33 66.67 33.33 +/- 0.75% center spread 1 0 1100 200.00 66.67 33.33 0 to +0.5% up spread 1 0 1101 166.67 66.67 33.33 0 to +0.5% up spread 1 0 1110 100.00 66.67 33.33 0 to +0.5% up spread 1 0 1111 133.33 66.67 33.33 0 to +0.5% up spread bit 6: 0 = hardware select; 1 = i 2 c select. default is off. bit 7: 0 = spread off; 1 = spread spectrum enable. default is off cpuclk agpclk pciclk spread percentage
7 ics94228 0447e?05/07/04 byte 1: cpu, active/inactive register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b1 4 , 2 41 0 c k l c u p c , 0 t k l c u p c 6 t i b8 3 , 9 31 0 c s c _ k l c u p c , 0 t s c _ k l c u p c 5 t i b61 z h m 8 4 4 t i b71 z h m 8 4 _ 4 2 3 t i b-1 ) k c a b d a e r ( 0 s f 2 t i b8 21 2 p g a 1 t i b7 21 1 p g a 0 t i b6 21 0 p g a byte 2: pci, active/inactive register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b0 21 7 k l c i c p 6 t i b8 11 6 k l c i c p 5 t i b7 11 5 k l c i c p 4 t i b6 11 4 k l c i c p 3 t i b4 11 3 k l c i c p 2 t i b3 11 2 k l c i c p 1 t i b1 11 1 k l c i c p 0 t i b0 11 0 k l c i c p notes: 1. inactive means outputs are held low and are disabled from switching. byte 4: watch dog register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-0 ) k c a b d a e r ( # 8 4 _ 4 2 l e s 6 t i b-0 ) k c a b d a e r ( 3 s f 5 t i b-0 : s u t a t s g o d h c t a w m r a l a = 1 l a m r o n = 0 4 t i b-11 b s s 3 t i b-13 s f 2 t i b-12 s f 1 t i b-11 s f 0 t i b-10 s f byte 5: vendor specific feature, active/inactive register (1= enable, 0 = disable) byte 3: pci, ref, active/inactive register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b91 f _ k l c i c p 6 t i b2 21 e _ 9 k l c i c p 5 t i b-1 ) k c a b d a e r ( 1 s f 4 t i b1 21 8 k l c i c p 3 t i b6 41 f _ f e r 2 t i b-1 ) k c a b d a e r ( 2 s f 1 t i b7 411 f e r 0 t i b8 410 f e r t i b# n i pd w pn o i t p i r c s e d 7 t i b-0 d i e c i v e d 6 t i b-0 5 t i b-0 4 t i b-1 3 t i b-0 d i r o d n e v 2 t i b-0 1 t i b-0 0 t i b-1 byte 6: vendor id1 , active/inactive register (1= enable, 0 = disable) note: don?t write into this register, writing into this register can cause malfunction t i b# n i pd w pn o i t p i r c s e d 7 t i b-0 e l b a n e g o d h c t a w p o t s : 0 t r a t s : 1 6 t i b-0 e l b a n e m a r g o r p n / m 5 t i b-0 f o n o i t a t n e s e r p e r l a m i c e d e h t o t d n o p s e r r o c s t i b 8 e s e h t g o d h c t a w e h t s m 1 r o s m 0 9 2 s e o g t i e r o f e b t i a w l l i w r e m i t e h t t e s e r d n a e d o m m r a l a o t . g n i t t e s e f a s e h t o t y c n e u q e r f x 8 s i p u r e w o p t a t l u a f e d . s d n o c e s 6 . 4 = s m 0 8 5 4 t i b-0 3 t i b-1 2 t i b-0 1 t i b-0 0 t i b-0
8 ics94228 0447e?05/07/04 byte 7: vendor id2, active/inactive register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-0 d i n o i s i v e r 6 t i b-0 d i n o i s i v e r 5 t i b-0 d i n o i s i v e r 4 t i b-0 d i n o i s i v e r 3 t i b-1 d i n o i s i v e r 2 t i b-1 d i n o i s i v e r 1 t i b-0 d i n o i s i v e r 0 t i b-0 d i n o i s i v e r byte 8: byte count register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-0 d e v r e s e r 6 t i b-0 d e v r e s e r 5 t i b-0 d e v r e s e r 4 t i b-0 d e v r e s e r 3 t i b-1 d e v r e s e r 2 t i b-0 d e v r e s e r 1 t i b-0 d e v r e s e r 0 t i b-0 d e v r e s e r byte 11: vco spread spectrum control register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-x 7 t i b m u r t c e p s d a e r p s 6 t i b-x 6 t i b m u r t c e p s d a e r p s 5 t i b-x 5 t i b m u r t c e p s d a e r p s 4 t i b-x 4 t i b m u r t c e p s d a e r p s 3 t i b-x 3 t i b m u r t c e p s d a e r p s 2 t i b-x 2 t i b m u r t c e p s d a e r p s 1 t i b-x 1 t i b m u r t c e p s d a e r p s 0 t i b-x 0 t i b m u r t c e p s d a e r p s byte 12: vco spread spectrum control register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-x d e v r e s e r 6 t i b-x d e v r e s e r 5 t i b-x d e v r e s e r 4 t i b-x 2 1 t i b m u r t c e p s d a e r p s 3 t i b-x 1 1 t i b m u r t c e p s d a e r p s 2 t i b-x 0 1 t i b m u r t c e p s d a e r p s 1 t i b-x 9 t i b m u r t c e p s d a e r p s 0 t i b-x 8 t i b m u r t c e p s d a e r p s byte 10: vco frequency control register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-x 8 t i b r e d i v i d o c v 6 t i b-x 7 t i b r e d i v i d o c v 5 t i b-x 6 t i b r e d i v i d o c v 4 t i b-x 5 t i b r e d i v i d o c v 3 t i b-x 4 t i b r e d i v i d o c v 2 t i b-x 3 t i b r e d i v i d o c v 1 t i b-x 2 t i b r e d i v i d o c v 0 t i b-x 1 t i b r e d i v i d o c v byte 9: vco frequency control register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-x 0 t i b r e d v i d o c v 6 t i b-x 6 t i b r e d v i d f e r 5 t i b-x 5 t i b r e d v i d f e r 4 t i b-x 4 t i b r e d v i d f e r 3 t i b-x 3 t i b r e d v i d f e r 2 t i b-x 2 t i b r e d v i d f e r 1 t i b-x 1 t i b r e d v i d f e r 0 t i b-x 0 t i b r e d v i d f e r
9 ics94228 0447e?05/07/04 byte 13: output skew control register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-0 l o r t n o c w e k s 0 t / 0 c k l c u p c 6 t i b-0 5 t i b-0 4 t i b-0 3 t i b-0 l o r t n o c w e k s c / t s c _ c k l c u p c 2 t i b-0 1 t i b-0 0 t i b-0 byte 14: output skew control register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-0 l o r t n o c w e k s ) 0 : 8 ( k l c i c p 6 t i b-0 5 t i b-1 4 t i b-0 3 t i b-0 l o r t n o c w e k s ) 0 : 2 ( p g a 2 t i b-0 1 t i b-0 l o r t n o c e t a r w e l s : e _ 9 k l c i c p 0 t i b-0 byte 15: output rise/fall time select register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-0 0 t k l c u p c 6 t i b-0 0 c k l c u p c 5 t i b-0 t s c _ t k l c u p c 4 t i b-0 c s c _ c k l c u p c 3 t i b-1 l o r t n o c e t a r w e l s : ) 0 : 2 ( p g a 2 t i b-0 1 t i b-0 l o r t n o c e t a r w e l s : ) 0 : 2 ( f e r 0 t i b-0 byte 16: output rise/fall time select register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-0 l o r t n o c e t a r w e l s : ) 0 : 3 ( k l c i c p 6 t i b-0 5 t i b-1 l o r t n o c e t a r w e l s : ) 4 : 8 ( k l c i c p 4 t i b-0 3 t i b-0 l o r t n o c e t a r w e l s : z h m 8 4 2 t i b-0 1 t i b-0 l o r t n o c e t a r w e l s : z h m 8 4 _ 4 2 0 t i b-0
10 ics94228 0447e?05/07/04 absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . 5.5v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . 0c to +70c storage temperature . . . . . . . . . . . . . . . . . . . . ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = 3.3 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units input high voltage v ih 2v dd + 0.3 v input low voltage v il v ss - 0.3 0.8 v input high current i ih v in = v dd 5ma input low current i il1 v in = 0 v; inputs with no pull-up resistors -5 ma input low current i il2 v in = 0 v; inputs with pull-up resistors -200 ma operating i dd3. 3op66 c l = 0 pf; select @ 66mhz supply current i dd3. 3op100 c l = 0 pf; select @ 100mhz i dd3. 3op133 c l = 0 pf; select @ 133mhz power down pd 600 ma input frequency f i v dd = 3.3 v; 12 14.318 16 mhz c in logic inputs 5 pf c inx x1 & x2 pins 27 45 pf clk stabilization 1 t stab from v dd = 3.3 v to 1% target freq. 3 ms t cpu-pci 2.3 2.6 ns t cpu-agp 300 550 ps 1 guaranteed by design, not 100% tested in production. 180 ma skew window input capacitance 1
11 ics94228 0447e?05/07/04 electrical characteristics - ref t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh5 i oh = -12 ma 2.4 v output low voltage v ol5 i ol = 9 ma 0.4 v output high current i oh5 v oh = 2.0 v -22 ma output low current i ol5 v ol = 0.8 v 16 ma rise time 1 t r5 v ol = 0.4 v, v oh = 2.4 v 1.3 4 ns fall time 1 t f5 v oh = 2.4 v, v ol = 0.4 v 1.4 4 ns duty cycle 1 d t5 v t = 1.5v 45 54 57 % 1 guaranteed by design, not 100% tested in production. electrical characteristics - cpuclk (open drain) t a = 0 - 70c; v dd = 3.3 v +/-5%; v ddl =2.5v+/-5%; cl = 20 pf (unless otherwise stated) parameter symbol min typ units output impedance z o w v v output low current i ol2b 18 ma rise time 1 , cpuclk t r2b 2.2 ns fall time 1 , cpuclk t f2b 1.3 ns duty cycle 1 d t2b 45 50 % skew 1 t sk2b 140 jitter, cycle-to-cycle 1 , cpuclk t jcyc-cyc2b 150 ps notes: 1 - guaranteed by design, not 100% tested in production. 2 - vdif specifies the minimum input differential voltages (vtr-vcp) required for switching, where vtr is the "t r 3 - vpullup(external) = 2.7v, min = vpullup(external)/2-150mv; max=(vpullup(external)/2)+150mv differential crossover volta g e 1 cpuclk(op en drain) v x note 3 1.2 0.4 0.2 v ol = 0.3v v ol = 20%, v oh = 80% v oh = 80%, v ol =20% v t = 50% v t = 50% v t = v x 200 250 55 v vpullup(external) + 0.6 v 1.7 v 1.4 vpullup(external) + 0.6 2.0 2.5 output low voltage differential voltage-dc 1 v di f note 2 vpull-up(external) differential voltage-ac 1 v di f note 2 termination to max 1 v ol2b vpull-up(external) 1.2 0.4 output high voltage v oh2b conditions v o = v x termination to
12 ics94228 0447e?05/07/04 electrical characteristics - pciclk t a = 0 - 70c; vdd = 3.3 v +/-5%; cl = 30 pf (unless otherwise stated) parameter symbol min typ max units output high voltage v oh1 2.6 v output low voltage v ol1 0.4 v output high current i oh1 -16 ma output low current i ol1 19 ma rise time 1 t r1 2.0 2.5 ns fall time 1 t f1 1.8 2.5 ns duty cycle 1 dt1 45 51 55 % jitter cycle-to-cycle 1 tj c y c-c y c1 130 500 ps skew1(window) tsk1 330 500 ps 1 guaranteed by design, not 100% tested in production. conditions i oh = -11 ma i ol = 9.4 ma v oh = 2.0 v v ol = 0.8 v v ol = 0.4 v, v oh = 2.4v v oh = 2.4v, v ol = 0.4v v t = 1.5 v v t = 1.5v v t = 1.5v electrical characteristics - pciclk_e t a = 0 - 70c; vdd = 3.3 v +/-5%; cl = 20 pf (unless otherwise stated) parameter symbol min typ max units output high voltage v oh1 2.6 v output low voltage v ol1 0.4 v output high current i oh1 -12 ma output low current i ol1 12 ma rise time 1 t r1 1.7 2.5 ns fall time 1 t f1 2.0 2.5 ns duty cycle 1 dt1 45 52 55 % jitter cycle-to-cycle 1 tj c y c-c y c1 100 500 ps pci_e to pci skew1 tsk1 2.3 2.7 ns 1 guaranteed by desi g n, not 100% tested in production. conditions i oh = -11 ma i ol = 9.4 ma v oh = 2.0 v v ol = 0.8 v v ol = 0.4 v, v oh = 2.4v v t = 1.5 v v t = 1.5v v t = 1.5v v oh = 2.4v, v ol = 0.4v
13 ics94228 0447e?05/07/04 electrical characteristics - 24mhz, 48mhz t a = 0 - 70c; vdd = 3.3 v +/-5%, vddl = 2.5 v +/-5%; cl = 20 pf (unless otherwise stated) parameter symbol min typ max units output high voltage v oh5 2.4 v output low voltage v ol5 0.4 v output high current i oh5 -22 ma output low current i ol5 16 ma rise time 1 tr 5 1.3 4 ns fall time 1 tf 5 1.3 4 ns duty cycle 1 dt 5 45 52 55 % jitter, cycle-to-cycle 1 tjcyc-cyc1 190 500 ps jitter, absolute 1 tjabs5 -1 1 ns 1 guaranteed b y desi g n, not 100% tested in production. conditions i oh = -16 ma i ol = 9 ma v oh = 2.0 v v ol = 0.8 v v t = 1.5 v v ol = 0.4 v, v oh = 2.4v v oh = 2.4 v, v ol = 0.4v vt = 1.5 v v t = 1.5 v
14 ics94228 0447e?05/07/04 fig. 1 shared pin operation - input/output pins the i/o pins designated by (input/output) on the ics94228 serve as dual signal functions to the device. during initial power-up, they act as input pins. the logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. at the end of power- on reset, (see ac characteristics for timing values), the device changes the mode of operations for these pins to an output function. in this mode the pins produce the specified buffered clocks to external loads. to program (load) the internal configuration register for these pins, a resistor is connected to either the vdd (logic 1) power supply or the gnd (logic 0) voltage potential. a 10 kilohm (10k) resistor is used to provide both the solid cmos programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. via to vdd clock trace to load series term. res. programming header via to gnd device pad 2k 8.2k figure 1 shows a means of implementing this function when a switch or 2 pin header is used. with no jumper is installed the pin will be pulled high. with the jumper in place the pin will be pulled low. if programmability is not necessary, than only a single resistor is necessary. the programming resistors should be located close to the series termination resistor to minimize the current loop area. it is more important to locate the series termination resistor close to the driver than the programming resistor.
15 ics94228 0447e?05/07/04 agp_stop# timing diagram notes: 1. all timing is referenced to the internal cpuclk. 2. agp_stop# is an asynchronous input and metastable conditions may exist. this signal is synchronized to the cpuclks inside the ics4228 . 3. all other clocks continue to run undisturbed. 4. pd# and pci_stop# are shown in a high (true) state. 5. only applies if mode pin latched 0 at power up. agp_stop# is an asychronous input to the clock synthesizer. it is used to turn off the agp clocks. for low power operation. agp_stop# is synchronized by the ics94228 . the agpclks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. agpclk on latency is less than agpclk and agpclk off latency is less than 3 agpclks. this function is available only with mode pin latched low. cpu_stop# timing diagram cpu_stop# is an asychronous input to the clock synthesizer. it is used to turn off the cpuclks for low power operation. cpu_stop# is synchronized by the ics94228 . all other clocks will continue to run while the cpuclks clocks are disabled. the cpuclks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. cpuclk on latency is less than 4 cpuclks and cpuclk off latency is less than 4 cpuclks. notes: 1. all timing is referenced to the internal cpuclk. 2. cpu_stop# is an asynchronous input and metastable conditions may exist. this signal is synchronized to the cpuclks inside the ics94228 . 3. all other clocks continue to run undisturbed. 4. pd# and pci_stop# are shown in a high (true) state. pciclk cpuclkt cpuclkt_cst cpuclkc cpuclkc_csc pd# (high) cpu_stop# internal cpuclk
16 ics94228 0447e?05/07/04 pd# timing diagram the power down selection is used to put the part into a very low power state without turning off the power to the part. pd# is an asynchronous active low input. this signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. internal clocks are not running after the device is put in power down. when pd# is active low all clocks need to be driven to a low value and held prior to turning off the vcos and crystal. the power up latency needs to be less than 3 ms. the power down latency should be as short as possible but conforming to the sequence requirements shown below. pci_stop# and cpu_stop# are considered to be don't cares during the power down operations. the ref and 48mhz clocks are expected to be stopped in the low state as soon as possible. due to the state of the internal logic, stopping and holding the ref clock outputs in the low state may require more than one clock cycle to complete. notes: 1. all timing is referenced to the internal cpuclk (defined as inside the ics94228 device). 2. as shown, the outputs stop low on the next falling edge after pd# goes low. 3. pd# is an asynchronous input and metastable conditions may exist. this signal is synchronized inside this part. 4. the shaded sections on the vco and the crystal signals indicate an active clock. 5. diagrams shown with respect to 133mhz. similar operation when cpu is 100mhz. cpuclkt cpuclkc pciclk vco crystal pd# pci_stop# timing diagram pci_stop# is an asynchronous input to the ics94228 . it is used to turn off the pciclk clocks for low power operation. pci_stop# is synchronized by the ics94228 internally. the minimum that the pciclk clocks are enabled (pci_stop# high pulse) is at least 10 pciclk clocks. pciclk clocks are stopped in a low state and started with a full high pulse width guaranteed. pciclk clock on latency cycles are only one rising pciclk clock off latency is one pciclk clock. notes: 1. all timing is referenced to the internal cpuclk (defined as inside the ics94228 device.) 2. pci_stop# is an asynchronous input, and metastable conditions may exist. this signal is required to be synchronized inside the ics94228. 3. all other clocks continue to run undisturbed. 4. cpu_stop# is shown in a high (true) state. cpuclk (internal) pciclk_f (internal) pciclk_f (free-running) cpu_stop# pciclk pci_stop#
17 ics94228 0447e?05/07/04 ordering information ics94228 y flf-t index area index area 12 1 2 n d h x 45 h x 45 e1 e seating plane seating plane a1 a e -c- - c - b .10 (.004) c .10 (.004) c c l 300 mil ssop package min max min max a 2.41 2.80 .095 .110 a1 0.20 0.40 .008 .016 b 0.20 0.34 .008 .0135 c 0.13 0.25 .005 .010 d e 10.03 10.68 .395 .420 e1 7.40 7.60 .291 .299 e h 0.38 0.64 .015 .025 l 0.50 1.02 .020 .040 n designation for tape and reel packaging lead free (optional) package type f = ssop revision designator (will not correlate with datasheet revision) device type prefix ics = standard device ics xxxx y f lf- t
idt.com | idt email | print contact idt | investors | press document search | package search | parametric search | cross reference search | green & rohs | calculators | thermal data | reliability & quality | military add to myidt [?] home > products > timing solutions > pc-notebook-server clocks > clock synthesizer by chipset vendor > desktop chipsets > 94228 94228 (desktop chipsets) description via kt266 style chipset market group pc clock additional info the ics94228 is a main clock synthesizer chip for amd-k7 based systems with via style chipset. this provides all clocks required for such a system. ? 1 - differential pair open drain cpu clocks @ 2.7v ? 1 - differential pair push-pull cpu clocks @ 2.5v ? 11 - pci including 1 free running and 1 early @ 3.3v ? 1 - 48mhz, @ 3.3v fixed ? 1 - 24/48mhz @ 3.3v ? 3 - ref @ 3.3v, 14.318mhz. you may also like... related orderable parts http://www.idt.com/?genid=94228 (1 of 2) [30-mar-2007 2:58:22 pm]
idt.com | idt attributes 94228bf 94228bflf 94228BFLFT 94228bft voltage 3.3 v (pv48) 3.3 v (pvg48) 3.3 v (pvg48) 3.3 v (pv48) package ssop 48 ssop 48 ssop 48 ssop 48 speed na na na na temperature c c c c status active active active active sample yes yes no no minimum order quantity 120 120 1000 1000 factory order increment 30 30 1000 1000 related documents type title size revision date datasheet 94228 datasheet 135 kb 03/24/2006 model - ibis 94228 ibis model 147 kb 03/24/2006 home | site map | about idt | press room | investor relations | trademark | privacy policy | careers | register | contact us use of this website signifies your agreement to the acceptable use and privacy policy. copyright 1997-2007 integrated device technology, inc. all rights reserved. node: www.idt.com http://www.idt.com/?genid=94228 (2 of 2) [30-mar-2007 2:58:22 pm]

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